1. Field of the Invention
The present invention relates to a memory mapping method in a data processing system.
2. Description of the Prior Art
Most data processing systems presently used provide the opportunity for increasing the capacity of the working memory in order to fulfill new requirements. This is commonly attained by arranging the working memory modularly; that is, by having a variable number of identical memory modules housed into a unit which is designed to contain a certain maximum number of modules. A memory module has a predetermined capacity (for instance 128K bytes) and is implemented with printed circuit boards of predetermined sizes and by a denoted number of standard integrated memory components. Because of rapid changes in technology, the manufacturers of data processing systems are faced with the problem of upgrading the working memory at minimum cost. Because of such progress in new integrated memory components which have greater and greater capacity, a memory module may be built which has a greater capacity than it had (for instance double or quadruple) while at the same time maintaining the size of its memory board unchanged. Thus the capacity of a working memory may be increased not only by increasing the number of memory modules, but also by utilizing memory modules of greater capacity. Moreover it is unnecessary to remove the smaller capacity modules already installed. In such a way it is possible to obtain a working memory with a capacity variable as a function of the number and type of modules, and in which modules of different capacity are present at the same time. However there is a problem in addressing such memories. Predetermined circuits are required that can address any of several modules of the working memory so that the several modules may be addressed as if they constitute an addressable continuous space of one memory only. Because in data processing systems processors, working memories and peripheral units are all interconnected via busses which define a common interface for several types of equipments, it is not possible to perform the required address conversion outside the working memory without affecting the interfaces of all the equipment. Such conversion must therefore occur within the working memory and must be performed with simple and fast circuits so as not to introduce unacceptable delays in the memory access times and further increase the complexity and the related cost of such circuits. A partial solution to this problem is described in U.S. Pat. No. 4,001,786. The circuit solution proposed by such patent is partial since it is relatively slow and requires a considerable number of hardware components, thus resulting in a complex and expensive memory. Another U.S. Patent Application Ser. No. 422,772, filed by the same Applicant on Sept. 24, 1982 (or the corresponding European Patent Application No. 82110396.7 published with No. 0080626 on June 8, 1983) describes a memory module selection apparatus which uses a logical selection network simpler and faster than the one described in the mentioned U.S. patent. In fact certain processing functions are installed on the central unit, which performs them once and for all during the initialization phase. In particular the modular memory sends to the central unit some information about the capacity of its constituent modules. The central unit processes such information and provides the memory with a set of information representative of the capacity of the first module, of the sum of the capacity of the first and second module, of the sum of the capacity of the first, second and third module, and so on for the total memory capacity. This information set is loaded into suitable registers of the module selection apparatus included into the memory. When the memory is addressed, a meaningful portion of the address is simultaneously compared, by several comparators, with the content of the several registers. The signals representative of the results of the several comparisons are applied to a decoder which selects one of the several memory modules. However the above-mentioned module selection apparatus still comprises registers, comparison circuits and a decoder and therefore is relatively complex and slow. These disadvantages are overcome by the present invention which allows the use of a smaller number of hardware components still keeping to a minimum the module selection delays.